Serial interfaces are typically used to conserve packaging and cable space as compared to parallel interfaces. Even though serial interfaces provide reduced board space, cable, and connection costs, they must still meet a system's performance requirements. In addition to providing high performance, the serial interfaces must also provide error detection and correction capabilities and minimize bus arbitration latencies, a component affecting the serial interface performance.
One such high performance serial interface is a serial RapidIO® interface which is a packet switched interconnect technology. (RapidIO® is a registered trademark of the RapidIO Trade Association.) The serial RapidIO® interface is an interconnect standard that allows a single lane (1×) or four lanes (4×) of serial data transfers, with each lane working at a multi-gigabit/second data rate. With the serial RapidIO® interface configured for four lanes, eight to ten cycles are typically needed to do lane alignment and clock compensation. The serial lanes are aligned to compensate for different serial interconnect delays going through the four serial lanes. Asynchronous first in first out memories (FIFOs) are use in the lane alignment process. Clock compensation is also used to compensate for clock frequency differences between two agents connected through a serial RapidIO® interconnect. A second asynchronous FIFO, working as an elastic buffer, is generally used for clock compensation. The reason for the eight to ten cycles of lane alignment latency is that lane alignment and clock compensation operations are done in two stages, with four to five cycles of latency in each stage. Consequently, there is a need to improve the lane alignment latency to improve the overall serial interface and system performance.